NET4EXA - Network for European Exascale Systems

ID Call: HORIZON-EUROHPC-JU-2023-INTER-02 Innovation Action in Low Latency and High Bandwidth Interconnects

Sapienza's role in the project: Affiliated entity

Scientific supervisor for Sapienza: Daniele De Sensi

Department: Computer Science

Project start date: September 1, 2024

Project end date: February 28, 2027

Abstract:

The NET4EXA project aims to create an advanced interconnect for HPC and AI systems, including application to Large Language Models, that will scale to hundreds of thousands of computing nodes. Building on the successful BXI (BullSequana eXascale Interconnect) European HPC Interconnect, NET4EXA will continue the development of the next generation of European Interconnects (BXIv3). The earlier versions BXIv1 and BXIv2 have been deployed in European supercomputers ranking among the TOP15. The project will showcase a fully functional Pilot at TRL 8, poised for adoption and integration into exascale and post-exascale European supercomputers.  The project will contribute by offering analysis and preliminary design for upcoming interconnect features, thus paving the way for continued progress in the field. NET4EXA will also prepare the subsequent version, BXIv4

Sapienza contributes to the NET4EXA project as an affiliated partner of CINECA, bringing strong expertise in high-performance computing and communication technologies. Our work focuses on the design and evaluation of the next-generation BXI interconnect (BXIv3 and BXIv4), including advanced features such as in-network collectives and TCP offload. We also contribute to the development and tuning of adaptive routing and congestion control mechanisms, key components for efficient and scalable communication. Sapienza is involved in designing topology-aware collective communication algorithms and assessing programming models like MPI to evaluate how well they can exploit BXI-specific capabilities such as non-contiguous data transfers, communication-computation overlap, and offloading. By combining hardware acceleration with software-level improvements, Sapienza helps uncover technical limitations and pushes forward the optimization of next-generation HPC interconnects.